Computer systems use a variety of means for displaying information on a display device. Such display devices typically include cathode my tube (CRT) display devices, liquid crystal devices, hard copy print devices, or other output devices accessible to the processor of the computer system. These display devices usually include frame buffers. A frame buffer is a portion of the computer system memory that has a predefined correspondence between a buffer memory location and a point on a display screen. The processor of the computer system is normally responsible for loading and maintaining the contents of a frame buffer memory.
Most computer systems include some form of Random Access Memory (RAM). The system memory of a large portion of computer systems typically includes Dynamic RAM (DRAM) devices. One type of DRAM used in system memories is a page mode DRAM. Page mode DRAMs allow an entire row of memory to be accessed by holding the row access strobe (RAS) signal active while strobing each of the column addresses with the column access strobe (CAS) until the entire row is accessed.
Frame buffer memories are usually implemented using Video RAM (VRAM) devices. One type of VRAM is the page mode VRAM, which is accessed in the same manner as that of the page mode DRAM. The processor of the computer system accesses VRAM in a similar manner to an access to any computer system memory (e.g., DRAM) by applying an address, various control signals and data to the input of the VRAM. However, unlike system memory or DRAM, VRAM devices usually include an additional output port to which a digital-to-analog converter (DAC) is connected. The DAC converts the data received from the VRAM from digital to analog for display. A CRT display is coupled to the DAC to receive the analog data and display the data. Display elements or picture elements (pixels) can be selectively enabled or disabled on the CRT display by outputting frame buffered data from the VRAM through the DAC and onto the CRT display. Rows of the display elements (also called scan lines) can be displayed using hardware within the VRAM, the DAC, and the CRT display. Because each scan line must be clocked out of VRAM separately, some control means must be present in the computer system for performing this display control function.
In current computer system implementations, two memory controllers are used: one for controlling DRAM devices (i.e., the system memory) and another for controlling VRAM devices (i.e., the frame buffer or display memory). Two memory controllers are necessary in prior art implementations because of the differences between controlling the DRAM and VRAM devices. For instance, the frame buffer output control function is not necessary for DRAM devices. However, many similarities exist in the control of DRAM and VRAM devices. The manner in which the processor accesses-to the two types of devices is virtually identical. Because of the many similarities in the control of DRAM and VRAM devices, some level of component, redundancy is introduced when two memory controllers are used. This redundancy is one factor contributing to the increased cost of the dual memory controller implementation.
In current computer systems, data is often moved between the system memory and the video, or graphics, memory. These data transfers are often referred to as screen-to-memory and memory-to-screen bit block, or fly-by, transfer operations. For example, in a windowing type application, where one particular window is to appear on top of another window, the data corresponding to the covered window in the screen is sent from the frame buffer to the main system memory, while the portion corresponding to the covering window is sent to the video memory to be displayed on the screen.
In prior art computer systems, the frame buffer is typically on a different bus than that of the system memory. Therefore, in order to perform screen-to-memory and memory-to-screen transfers, the device or circuitry controlling the transfer has to become the bus owner of more than one bus to transfer the data (i.e., the system bus and the graphics bus). The bus ownership and transfer of data using two disjoint or isolated locations involves much overhead (i.e., multi-bus arbitration, bus bridge latencies and bus bandwidths) and, thus, causes the transfers to occur very slowly. The transfers are typically slow because the I/O bus on which the frame buffer transfers data is usually slower than most buses (e.g., graphics buses).
When transfers are performed in computer systems, the transfers normally include reading data from one location and writing it to another location using a memory controller. One common transfer occurs between a system memory location and an I/O location. In a typical memory system, in order to perform a transfer to an I/O device, an access occurs to obtain the data from one location (i.e., the source location), and then another access to the other location (i.e., the destination location) is required in order to complete the transfer. For instance, the CPU of the computer system would perform an access to a memory device on the bus to obtain data (i.e., a read operation). The CPU would then perform a write operation, such that the data is sent to its destination I/O device. In this situation, since both devices share the same buses, only one memory address is utilized (i.e., required), for the address is required only when reading the data. A special address is not required for each of the I/O devices due to the use of data acknowledge signals (DACKs) that are driven by the direct memory access (DMA) controller in the system. These DACKs are dedicated lines which select a particular memory element and/or I/O device for a data access.
In the prior art, memory-to-memory transfers are performed. However, one problem associated with memory-to-memory transfers in the prior art is that the memories usually share the same address and data buses, yet use different addresses or addressing schemes. Because an address in one memory may not correspond to the same address in the other memory, two separate accesses must be performed. In other words, when transferring data from one address in a first memory to a different address in a second memory while sharing the same address and data buses, two separate accesses must occur. First, a read cycle using the address location in the first memory must be performed to obtain the data. Once the data has been obtained, a write cycle must be completed to write the data into different data address in the second memory.
As will be shown, the present invention provides a method and apparatus for performing fly-by bit block transfers between different portions of the same memory. The present invention also provides for fly-by transfers between VRAM and DRAM devices in the same memory. The present invention provides a method and apparatus for performing fly-by bit block transfers in a linear frame buffer, such that data can be transferred between the computer display screen and the system memory without using the slower system bus. Likewise, the present invention allows for transfers to occur between the video memory and system memory while using shared data and address buses.